1. Technical Field
The invention relates generally to semiconductor devices, and more specifically, to chip-on-chip interconnections in semiconductor devices.
2. Background Art
In the past, semiconductor devices built with different technologies were fabricated on separate wafers, diced, and then connected together by mounting the devices on a substrate. Recently, the merging of DRAM and logic, and other dissimilar semiconductor technologies has been headed towards connecting one chip directly to another chip through solder ball connections, such as C4 (controlled collapse chip connection) connections. This structure, known as a face-to-face chip-on-chip (chip 1/chip2) structure, provides a large number of I/O's between the two chips and is shown in the following IBM Technical Disclosure Bulletins: Vol. 28 No. 2, July 1985 "Mated Array Chip Configuration", pgs. 811-812; and Vol. 25 No. 10, March 1983 "Chip-On-Chip Module for Assembly" by Spector et al., pgs. 5315-5316. Although the chip1/chip2 structure of the aforementioned bulletins and other similar structures are joined through C4 technology, there is a limit to how the connections can be made between the chips as well as connections made to the outside package. Thus, other chip-on-chip connections, such as wirebonding, are necessary to connect the chip1/chip2 structure to other chips or to the outside package. These other connections may not be as easily manufactured or as durable as the C4 solder ball connection.